Philips Security Camera TDA8783 User Manual

INTEGRATED CIRCUITS  
DATA SHEET  
TDA8783  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
Product specification  
2002 Oct 23  
Supersedes data of 1999 Jun 25  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
QUICK REFERENCE DATA  
SYMBOL  
VCCA  
PARAMETER  
analog supply voltage  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
4.75  
4.75  
2.5  
5
5.25  
5.25  
5.25  
95  
V
VCCD  
VCCO  
ICCA  
digital supply voltage  
5
V
digital outputs supply voltage  
analog supply current  
3
V
78  
18  
1
mA  
mA  
mA  
ICCD  
ICCO  
digital supply current  
20  
digital outputs supply current  
fCLK = 27 MHz;  
CL = 20 pF; ramp input  
ADCres  
Vi(CDS)(p-p)  
GCDS  
ADC resolution  
40  
10  
400  
6
bits  
CDS input voltage (peak-to-peak value)  
CDS output amplifier gain  
maximum clock frequency  
1200 mV  
dB  
fCLK(max)  
fcut(CDS) = 120 MHz;  
fcut(AGC) = 54 MHz  
MHz  
AGCdyn  
Ntot(rms)  
AGC dynamic range  
30  
dB  
total noise from CDS input to ADC output gain = 4.5 dB;  
(RMS value)  
0.125  
LSB  
fcut(CDS) = 120 MHz;  
cut(AGC) = 40 MHz  
f
Ptot  
total power consumption  
483  
mW  
2002 Oct 23  
3
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
BLOCK DIAGRAM  
V
V
V
CLPOB  
1
DGND2  
40  
CCA3  
45  
CCD2  
39  
IND INP AGND3  
SHD  
44  
SHP  
43  
CLPDM  
42  
CLK  
41  
OE  
38  
CCO  
37  
47  
46  
48  
36  
OGND  
TRACK-  
TRACK-  
CLOCK  
AND-HOLD  
AND-HOLD  
GENERATOR  
35  
34  
33  
32  
31  
30  
29  
28  
27  
TRACK-  
AND-HOLD  
D9  
D8  
8
CPCDS  
CLAMP  
CLAMP  
5
AGND1  
4-BIT DAC  
CUT-OFF  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
ref1  
4
OUTPUTS  
BUFFER  
AMPOUT  
6 dB  
10-BIT ADC  
2
AGND4  
TDA8783  
7
1
AGCOUT  
AGC  
1
4-BIT DAC  
CUT-OFF  
6
V
CCA1  
9-BIT DAC  
9
AGND5  
10  
26  
25  
3
ADCIN  
D0  
DGND1  
OFDOUT  
12  
11  
+
-
V
ref  
CLPADC  
8-BIT DAC  
SERIAL  
INTERFACE  
10-BIT DAC  
REGULATOR  
16 17 18  
13  
14  
15  
22  
SEN  
21  
20  
24  
19  
23  
V
V
DACOUT  
CCA2  
V
AGND6  
STDBY  
DEC1  
SDATA  
SCLK  
CCD1  
RT  
MGM491  
V
AGND2  
RB  
Fig.1 Block diagram.  
4
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
PINNING  
SYMBOL  
PIN  
DESCRIPTION  
CLPOB  
AGND4  
OFDOUT  
AMPOUT  
AGND1  
VCCA1  
1
2
clamp pulse input at optical black  
analog ground 4  
3
analog output of the additional 8-bit control DAC (controlled via the serial interface)  
CDS amplifier output (fixed gain = 6 dB)  
analog ground 1  
4
5
6
analog supply voltage 1  
AGCOUT  
CPCDS  
AGND5  
ADCIN  
7
AGC amplifier signal output  
8
clamp storage capacitor pin  
9
analog ground 5  
10  
11  
12  
ADC analog signal input from AGCOUT via a short circuit  
clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground)  
CLPADC  
Vref  
ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or connected to  
ground via a capacitor)  
DACOUT  
AGND2  
VCCA2  
VRB  
13  
14  
15  
16  
17  
18  
19  
20  
DAC output for ADC clamp level  
analog ground 2  
analog supply voltage 2  
ADC reference voltage (BOTTOM) code 0  
ADC reference voltage (TOP) code 1023  
decoupling 1 (decoupled to ground via a capacitor)  
analog ground 6  
VRT  
DEC1  
AGND6  
SDATA  
serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;  
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby  
mode per block and edge pulse control); see Fig.3, Fig.4 and Table 1  
SCLK  
SEN  
21  
22  
serial clock input for the control DACs and their serial interface; see Fig.3, Fig.4 and Table 1  
enable input for the serial interface shift register (active when SEN = logic 0); see Fig.3, Fig.4 and  
Table 1  
STDBY  
VCCD1  
DGND1  
D0  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
standby control (active HIGH); all the output bits are logic 0 when standby is enabled  
digital supply voltage 1  
digital ground 1  
ADC digital output 0 (LSB)  
ADC digital output 1  
D1  
D2  
ADC digital output 2  
D3  
ADC digital output 3  
D4  
ADC digital output 4  
D5  
ADC digital output 5  
D6  
ADC digital output 6  
D7  
ADC digital output 7  
D8  
ADC digital output 8  
D9  
ADC digital output 9 (MSB)  
digital output ground  
OGND  
2002 Oct 23  
5
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SYMBOL  
VCCO  
PIN  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
DESCRIPTION  
digital output supply voltage  
OE  
output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)  
VCCD2  
DGND2  
CLK  
digital supply voltage 2  
digital ground 2  
ADC clock input  
CLPDM  
SHP  
clamp pulse input at dummy pixel  
pre-set sample-and-hold pulse input  
data sample-and-hold pulse input  
analog supply voltage 3  
pre-set input signal from CCD  
data input signal from CCD  
analog ground 3  
SHD  
VCCA3  
INP  
IND  
AGND3  
1
2
36 OGND  
35  
CLPOB  
AGND4  
D9  
34 D8  
33  
OFDOUT  
AMPOUT  
AGND1  
3
4
D7  
32 D6  
31  
5
6
V
D5  
CCA1  
TDA8783HL  
AGCOUT  
CPCDS  
AGND5  
ADCIN  
7
30 D4  
29 D3  
28 D2  
27 D1  
8
9
10  
11  
12  
26  
CLPADC  
D0  
V
25 DGND1  
ref  
MGM492  
Fig.2 Pin configuration.  
6
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
VCCA  
PARAMETER  
analog supply voltage  
CONDITIONS  
note 1  
MIN.  
0.3  
0.3  
MAX.  
+7.0  
UNIT  
V
V
V
VCCD  
VCCO  
VCC  
digital supply voltage  
output stages supply voltage  
supply voltage difference  
between VCCA and VCCD  
between VCCA and VCCO  
between VCCD and VCCO  
input voltage  
note 1  
note 1  
+7.0  
+7.0  
0.3  
1.0  
1.0  
1.0  
0.3  
+1.0  
+4.0  
+4.0  
+7.0  
VCCD  
V
V
V
V
V
Vi  
referenced to AGND  
referenced to DGND  
VCLK(p-p)  
AC input voltage for switching  
(peak-to-peak value)  
Io  
output current  
10  
mA  
°C  
°C  
°C  
Tstg  
Tamb  
Tj  
storage temperature  
ambient temperature  
junction temperature  
55  
20  
+150  
+75  
150  
Note  
1. The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 and +7.0 V provided that the supply  
voltage difference VCC remains as indicated.  
HANDLING  
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is  
desirable to take normal precautions appropriate to handling integrated circuits.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
VALUE  
UNIT  
Rth(j-a)  
thermal resistance from junction to ambient in free air  
76  
K/W  
2002 Oct 23  
7
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
CHARACTERISTICS  
VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 27 MHz; Tamb = 25 °C; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
VCCA  
VCCD  
VCCO  
ICCA  
analog supply voltage  
digital supply voltage  
4.75  
5
5.25  
5.25  
5.25  
95  
V
4.75  
2.5  
5
V
digital outputs supply voltage  
analog supply current  
3
V
78  
18  
1
mA  
mA  
mA  
ICCD  
digital supply current  
20  
ICCO  
digital outputs supply current  
CL = 20 pF on all data  
outputs; ramp input  
Digital inputs  
CLOCK INPUT: CLK (REFERENCED TO DGND)  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input impedance  
0
46  
1
0.8  
VCCD  
+1  
20  
V
2.0  
1  
V
VCLK = 0.8 V  
VCLK = 2.0 V  
fCLK = 27 MHz  
fCLK = 27 MHz  
µA  
µA  
kΩ  
pF  
IIH  
Zi  
Ci  
input capacitance  
INPUTS: SHP AND SHD  
VIL  
VIH  
IIL  
LOW-level input voltage  
0
6  
0
0.8  
VCCD  
V
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
2.0  
V
VIL = 0.8 V  
VIH = 2.0 V  
µA  
µA  
IIH  
INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC  
VIL  
VIH  
Ii  
LOW-level input voltage  
HIGH-level input voltage  
input current  
0
0.8  
V
2.0  
2  
VCCD  
+2  
V
µA  
Correlated Double Sampling (CDS); note 1  
Vi(CDS)(p-p)  
CDS input amplitude pin 47  
(peak-to-peak value)  
400  
1200 mV  
ICPCDS, IINP,  
IIND  
input current pins 8, 46 and 47  
2  
8
+2  
µA  
tCDS(min)  
CDS control pulses minimum  
active time  
fi(CDS1,2) = fCLK(pix)  
;
ns  
Vi(CDS)(p-p) = 600 mV  
black-to-white transition in  
1 pixel (±1 LSB typ.);  
fcut(CDS) = 120 MHz;  
fcut(AGC) = 54 MHz  
thd1  
hold time INP compared to control see Fig.5  
pulse SHP  
1
ns  
2002 Oct 23  
8
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SYMBOL  
thd2  
PARAMETER  
CONDITIONS  
see Fig.5  
MIN.  
TYP. MAX. UNIT  
hold time of IND compared to  
control pulse SHD  
1
ns  
tset(CDS)  
CDS settling time  
see Fig.12; control DAC  
4 bits input code;  
AGC gain = 0 dB;  
f
cut(AGC) = 54 MHz;  
Vi(CDS) = 600 mV (p-p)  
black-to-white transition in  
1 pixel (±1 LSB typ.)  
0000  
0001  
0010  
0011  
0100  
0111  
1000  
1011  
1111  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
21  
42  
52  
82  
94  
195  
219  
280  
Amplifier outputs  
GAMPOUT  
output amplifier gain  
ZAMPOUT output amplifier impedance  
6
dB  
300  
2.4  
VAMPOUT(p-p) output amplifier dynamic voltage  
(peak-to-peak value)  
V
VAMPOUT(bl)  
output amplifier black level  
voltage  
1.5  
2000  
Vref  
5
V
VAGCOUT(p-p) AGC output amplifier dynamic  
voltage level (peak-to-peak value)  
mV  
V
VAGCOUT(bl)  
AGC output amplifier black level  
voltage  
Vref connected to DACOUT  
ZAGCOUT  
AGC output amplifier output  
impedance  
at 10 kHz  
IAGCOUT  
AGC output static drive current  
minimum gain of AGC circuit  
static  
4.5  
1
mA  
dB  
GAGC(min)  
AGC DAC input code = 00  
(9-bit control); see Fig.7  
GAGC(max)  
fcut(AGC)  
maximum gain of AGC circuit  
cut-off frequency AGC  
AGC DAC input code 319  
34.5  
dB  
(9-bit control); see Fig.7  
4-bit control DAC  
input code = 00  
54  
4
MHz  
MHz  
input code = 15  
other codes see Fig.13  
2002 Oct 23  
9
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SYMBOL  
Clamps  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
gm(ADC)  
gm(CDS)  
ADC clamp transconductance  
CDS clamp transconductance  
at clamp level  
7
mS  
mS  
at clamp level  
1.5  
Analog-to-Digital Converter (ADC)  
fCLK(max)  
tCPH  
maximum clock frequency  
clock pulse width HIGH  
clock pulse width LOW  
40  
12  
12  
0.5  
MHz  
ns  
tCPL  
ns  
SRCLK  
clock input slew rate (rising and  
falling edge)  
10% to 90%  
V/ns  
Vi(ADC)(p-p)  
VRB  
ADC input voltage level  
(peak-to-peak value)  
2
V
V
V
ADC reference voltage output  
code 0  
1.5  
3.5  
VRT  
ADC reference voltage output  
code 1023  
IADCIN  
INL  
ADC input current  
2  
+120 µA  
integral non-linearity  
differential non-linearity  
sampling delay time  
ramp input  
ramp input  
±0.6  
±0.2  
±1.5  
LSB  
DNL  
td(s)  
±0.75 LSB  
5
ns  
Total chain characteristics (CDS + AGC + ADC)  
td  
delay between SHD and CLK  
50% at rising edges  
30  
ns  
CLK and SHD: transition full  
scale code 0 to 1023;  
f
cut(CDS) = 120 MHz;  
fcut(AGC) = 54 MHz;  
Vi(CDS) = 600 mV  
Ntot(rms)  
total output noise (RMS value)  
fcut(CDS) = 120 MHz;  
fcut(AGC) = 40 MHz; note 2  
GAGC = 4.5 dB  
200  
0.125  
1.6  
LSB  
LSB  
GAGC = 34.5 dB  
Voffset(fl-d)  
maximum offset between CCD  
floating level and CCD dark pixel  
level  
+200 mV  
Vn(i)(eq)(rms)  
equivalent input noise voltage  
(RMS value)  
AGC gain = 34.5 dB  
AGC gain = 4.5 dB  
125  
150  
µV  
µV  
Digital-to-Analog Converter (OFDOUT)  
VOFDOUT(p-p) additional 8-bit control DAC  
(OFD) output voltage  
1.4  
V
(peak-to-peak value)  
VOFDOUT(0)  
DC output voltage for code 0  
2.3  
3.7  
V
V
VOFDOUT(255) DC output voltage for code 255  
2002 Oct 23  
10  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
ZOFDOUT  
additional 8-bit control DAC  
(OFD) output impedance  
2000  
IOFDOUT  
OFD output current drive  
static  
50  
µA  
ADC clamp control DAC (see Fig.8)  
VDACOUT(p-p) ADC clamp 10-bit control DAC  
output voltage (peak-to-peak  
value)  
1
V
VDACOUT  
DC output voltage  
code 0  
1.5  
2.5  
V
V
code 1023  
ZDACOUT  
ADC clamp control DAC output  
impedance  
250  
IDACOUT  
DAC output current drive  
static  
±5  
±5  
50  
µA  
LSB  
LSB  
OFELOOP  
maximum offset error of  
DAC + ADC clamp loop  
code 0  
code 1023  
Digital outputs (fCLK = 40 MHz; CL = 20 pF); note 3  
VOH  
VOL  
IOZ  
HIGH-level output voltage  
LOW-level output voltage  
output current in 3-state mode  
output hold time  
IOH = 1 mA  
IOL = 1 mA  
VCCO 0.5 −  
VCCO  
0.5  
+20  
V
0
V
0 V < Vo < VCCO  
20  
8
µA  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
to(h)  
to(d)  
output delay time  
CL = 20 pF; VCCO = 5 V  
CL = 10 pF; VCCO = 5 V  
CL = 20 pF; VCCO = 3 V  
CL = 10 pF; VCCO = 3 V  
CL = 20 pF; VCCO = 2.5 V  
CL = 10 pF; VCCO = 2.5 V  
17  
15  
20  
17  
22  
18  
23  
21  
29  
25  
33  
28  
Serial interface  
fSCLK(max)  
maximum frequency of serial  
interface  
5
MHz  
Notes  
1. More information about CDS related signals is available in the following figures: The clamp current for pin CPCDS is  
given in Fig. 9, clamp current for pins IND and INP in Fig 10 and for clamp current for pin Vref in Fig 11. The CDS  
output amplitude is shown in Fig. 14  
2. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise  
contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are  
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.  
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise  
is taken into account as no signal is input. Figure15 gives noise figure graphs with signal input.  
3. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the  
output delay timings (to(d)), see Fig.5.  
2002 Oct 23  
11  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SDATA  
SCLK  
SHIFT REGISTER  
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2  
LSB  
MSB  
10  
LATCH  
SEN  
SELECTION  
8
9
8
7
10  
(D7 to D0)  
(D8 to D0)  
(D7 to D0)  
(D6 to D0)  
(D9 to D0)  
CLAMP  
REFERENCE  
LATCHES  
PARTIAL  
STANDBY  
AND EDGE  
OFD  
LATCHES  
FREQUENCY  
LATCHES  
AGC GAIN  
LATCHES  
8-bit DAC  
AGC control  
frequency  
control  
standby  
control  
10-bit DAC  
MGM515  
CDS and AGC  
or edge clocks  
Fig.3 Serial interface block diagram.  
t
SDATA  
su2  
t
hd4  
MSB  
A0  
LSB  
D3  
A2  
A1  
D9  
D8  
D7  
D6  
D5  
D4  
D2  
D1  
D0  
SCLK  
SEN  
MGE373  
t
t
su1  
hd3  
t
su3  
tsu1 = tsu2 = tsu3 = 4 ns (min.); thd3 = thd4 = 4 ns (min.).  
Fig.4 Loading sequence of control DACs input data via the serial interface.  
12  
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
Table 1 Serial interface programming  
ADDRESS BITS  
DATA BITS D9 to D0  
OFD output control (D7 to D0).  
A2  
A1  
A0  
0
0
0
0
0
1
Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for  
CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.  
0
0
1
1
0
1
AGC gain control (D8 to D0).  
Partial standby controls for power consumption optimization. Only the 4 LSBs  
(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and  
clock ADC:  
D0 = 1: CDS + AGC in standby; ICCA + ICCD = 35 mA  
D1 = 1: OFD DAC in standby; ICCA + ICCD = 95 mA  
D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;  
ICCA + ICCD = 95.5 mA  
D3 = 1: SHP and SHD activated with falling edge (for positive pulse)  
D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1  
D5 = 0: CLKADC activated with falling edge  
D6 must be set to logic 0.  
1
0
0
Clamp reference DAC (D9 to D0).  
Note  
1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref.  
Vref is connected to ground via a capacitor.  
Table 2 Standby selection  
STDBY  
DATA BITS D9 to D0  
ICCA + ICCD (TYP.)  
4 mA  
1
0
LOW  
active  
96 mA  
2002 Oct 23  
13  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
IND  
N
N + 1  
N + 2  
N + 3  
t
SHP  
1.4 V  
CDS  
t
n(IN; SHP)  
1.4 V  
SHD  
t
t
n(IN; SHD)  
d
t
CLK  
1.4 V  
CPH  
t
t
o(d)  
d(s)  
N
ADCIN  
t
o(h)  
90%  
N 3  
N 2  
DATA  
N 1  
N
10%  
MGR395  
Fig.5 Pixel frequency timing diagram.  
2002 Oct 23  
14  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
1 pixel  
1 pixel  
AGCOUT  
VIDEO  
OPTICAL BLACK  
HORIZONTAL FLYBLACK  
DUMMY  
VIDEO  
CLPDM  
CLPADC  
WINDOW  
CLPDM  
CLPADC  
WINDOW  
CLPOB  
(active HIGH)  
CLPOB  
WINDOW  
CLPDM  
(1)  
(active HIGH)  
CLPADC  
(active HIGH)  
(1)  
MGR396  
(1) When dummy pixels are not available.  
Fig.6 Line frequency timing diagram.  
2002 Oct 23  
15  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
MGM507  
handbook, halfpage  
34.5  
G
AGC  
(dB)  
4.5  
0
319  
511  
AGC control DAC input code  
Fig.7 AGC gain as a function of DAC input code.  
MGM508  
3.7  
2.5  
OFD DAC  
voltage  
output  
(V)  
ADC CLAMP DAC  
voltage  
output  
(V)  
2.3  
1.5  
255  
1023  
0
0
OFD control DAC input code  
ADC CLAMP control DAC input code  
Fig.8 DAC voltage output as a function of DAC input code.  
16  
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
I
handbook, halfpage  
(µA)  
+100  
0
V (V)  
2.00  
100  
200 mV  
MGR397  
Fig.9 Typical clamp current for pin CPCDS.  
I
handbook, halfpage  
(µA)  
+300  
0
V (V)  
2.85  
300  
400 mV  
MGR398  
Fig.10 Typical clamp current for pins IND and INP.  
I
handbook, halfpage  
(µA)  
+200  
0
V
V (V)  
ref  
200  
400 mV  
MGR399  
Fig.11 Typical clamp current for pin Vref.  
17  
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
MGR441  
160  
300  
f
t
cut  
set  
(MHz)  
(ns)  
250  
120  
(2)  
(3)  
(4)  
200  
150  
100  
50  
80  
(1)  
40  
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4-bit control DAC input code  
(1) fcut  
.
(2) tset (10 bits accuracy).  
(3) tset (9 bits accuracy).  
(4)  
tset (8 bits accuracy).  
Fig.12 CDS settling time and bandwidth.  
2002 Oct 23  
18  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
MGR401  
60  
f
cut  
(MHz)  
40  
20  
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4-bit control DAC input code  
Fig.13 AGC bandwidth.  
MGR442  
1.6  
(1)  
(2)  
V
o(CDS)(p-p)  
(V)  
1.2  
(3)  
(4)  
(5)  
(6)  
0.8  
0.4  
0
0
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
V
(V)  
i(CDS)(p-p)  
(1) tset(CDS) = 12 ns  
(2) tset(CDS) = 10 ns  
(3) tset(CDS) = 8 ns  
(4) tset(CDS) = 7 ns  
(5) tset(CDS) = 6 ns  
(6) tset(CDS) = 5 ns  
Fig.14 CDS output.  
19  
2002 Oct 23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
MGR443  
3
N
tot(rms)  
(LSB)  
(1)  
2
(2)  
(3)  
(4)  
1
0
(5)  
(6)  
00  
40  
80  
C0  
100  
13F  
code  
(dB)  
(4.5)  
(10.5)  
(16.5)  
(22.5)  
(28.5)  
(34.5)  
G
AGC  
(1) fpix = 27 MHz; control DAC = 00H; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz.  
(2) fpix = 18 MHz; control DAC = 10H; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz.  
(3) fpix = 10 MHz; control DAC = 31H; fcut(CDS) = 80 MHz; fcut(AGC) = 30 MHz.  
(4) fpix = 5 MHz; control DAC = 43H; fcut(CDS) = 35 MHz; fcut(AGC) = 12 MHz.  
(5) fpix = 1 MHz; control DAC = F8H; fcut(CDS) = 6 MHz; fcut(AGC) = 4 MHz.  
(6)  
fpix = 375 kHz; control DAC = FFH; fcut(CDS) = 4 MHz; fcut(AGC) = 4 MHz.  
Fig.15 Output noise (RMS value).  
2002 Oct 23  
20  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
APPLICATION INFORMATION  
5.0 V  
5.0 V 2.5 to 5.25 V  
CCD  
(3)  
(3)  
(3)  
220  
nF  
from timing  
generator  
48 47 46 45 44 43 42 41 40 39 38 37  
CLPOB  
AGND4  
OGND  
D9  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
2
OFDOUT  
AMPOUT  
AGND1  
D8  
3
D7  
4
D6  
5
(3)  
V
D5  
CCA1  
6
5.0 V  
TDA8783  
AGCOUT  
CPSDS  
AGND5  
ADCIN  
D4  
7
1 µF  
D3  
8
D2  
9
D1  
10  
11  
12  
1 µF  
CLPADC  
D0  
V
DGND1  
ref  
13 14 15 16 17 18 19 20 21 22 23 24  
(2)  
(1)  
100  
nF  
2.2  
nF  
serial  
interface  
(3)  
5.0 V  
5.0 V  
1
nF  
1
(3)  
MGM504  
nF  
Depending on the application, the following connections must be made:  
(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface  
(clamp ADC activated).  
(2) Clamp ADC not activated, direct connection from DACOUT to Vref  
.
(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.  
Fig.16 Application diagram.  
2002 Oct 23  
21  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
Power and grounding recommendations  
In a two-ground system, in order to minimize the noise  
from package and die parasitics, the following  
recommendations must be implemented:  
Care must be taken to minimize noise when designing a  
printed-circuit board for applications such as PC cameras,  
surveillance cameras, camcorders and digital still  
cameras.  
The ground pin associated with the digital outputs must  
be connected to the digital ground plane and special  
care should be taken to avoid feedthrough in the analog  
ground plane. The analog and digital ground planes  
must be connected with an inductor as close as possible  
to the IC package, in order to have the same DC voltage  
on the ground planes.  
For the front-end integrated circuit, the basic rules of  
printed-circuit board design and implementation of analog  
components (such as classical operational amplifiers)  
must be taken into account, particularly with respect to  
power and ground connections.  
The digital output pins and their associated lines should  
be shielded by the digital ground plane, which can be  
used as return path for the digital signals.  
The connections between CCD interface and CDS input  
should be as short as possible and a ground ring  
protection around these connections can be beneficial.  
Decoupling capacitors are necessary on all supply pins as  
shown in Fig.16.  
Separate analog and digital supplies provide the best  
performance. If it is not possible to do this on the board,  
then decouple the analog supply pins effectively from the  
digital supply pins. The decoupling capacitors must be  
placed as close as possible to the IC package.  
2002 Oct 23  
22  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
PACKAGE OUTLINE  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v M  
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.60  
mm  
0.25  
0.5  
1.0  
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
99-12-27  
00-01-19  
SOT313-2  
136E05  
MS-026  
2002 Oct 23  
23  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
Introduction to soldering surface mount packages  
Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
Reflow soldering  
The footprint must incorporate solder thieves at the  
downstream end.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Manual soldering  
Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
2002 Oct 23  
24  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE(1)  
WAVE  
not suitable  
REFLOW(2)  
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA  
suitable  
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)  
HVSON, SMS  
suitable  
PLCC(4), SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
suitable  
suitable  
not recommended(4)(5) suitable  
not recommended(6)  
suitable  
Notes  
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy  
from your Philips Semiconductors sales office.  
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder  
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,  
the solder might be deposited on the heatsink surface.  
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not  
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2002 Oct 23  
25  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2002 Oct 23  
26  
 
Philips Semiconductors  
Product specification  
40 Msps, 10-bit analog-to-digital  
interface for CCD cameras  
TDA8783  
NOTES  
2002 Oct 23  
27  
 
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: [email protected].  
© Koninklijke Philips Electronics N.V. 2002  
SCA74  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
753504/03/pp28  
Date of release: 2002 Oct 23  
Document order number: 9397 750 10176  
 

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